① 求EDA用VHDL语言的程序设计，急急急！给高分！（要求在Quartus Ⅱ中完成一个正弦信号发生器,详见提问）
在Quartus Ⅱ中完成一个正弦信号发生器的设计。系统可由五部分组成，如下图所示：嵌入式锁相环、分频器、带有清零、使能功能的数据计数器（地址发生器）、存储数据的ROM、D/A和滤波电路。
我是初学者，虽然还不会做这个东西。但是一定不能急，在网上搜也不可能直接得到答案。还是沉下来自己慢慢扣吧，没有量的积累是不会有质的飞跃的。我会分阶段进行：第一步：在网络文库中查各种计数器的资料；
第二步：分频器可用计数器和VHDL直接写出；
第三步：8为DA芯片非常好用，要敢于试验；
第四步：看书查资料直接找相关资料；
网络查资料非常方便，但是结果要靠你自己总结！
② 求eda数字钟设计程序
1.Topclock（元件例化 顶层文件）
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity topclock is
Port(clk,clr,en,m1,h1:in std_logic;
alarm:out std_logic;
secs,secg,mins,ming,hours,hourg:buffer std_logic_vector(3 downto 0));
End;
2. 秒模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
end SECOND;
architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clr='1' then
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";
if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
sec1<=cnt1;
sec0<=cnt0;
end process;
end SEC;
3.分模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
end MINUTE;
architecture MIN of MINUTE is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";
if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
min1<=cnt1;
min0<=cnt0;
end process;
end MIN;
4.时模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;
h1,h0:out std_logic_vector(3 downto 0));
end HOUR;
architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";
cnt0:="0000";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;
end process;
end hour_arc;
----5.扫描模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;
sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);
ut:out std_logic_vector(3 downto 0);
sel:out std_logic_vector(2 downto 0));
end SELTIME;
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0);
begin
sel<=count;
process(clk)
begin
if(clk'event and clk='1') then
if(count>="101") then
count<="000";
else
count<=count+1;
end if;
end if;
case count is
when"000"=>ut<= sec0;
when"001"=>ut<= sec1;
when"010"=>ut<= min0;
when"011"=>ut<= min1;
when"100"=>ut<=h0;
when others =>ut<=h1;
end case;
end process;
end fun;
6.显示模块程序
library ieee;
use ieee.std_logic_1164.all;
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0));
end DISPLAY;
architecture disp_are of DISPLAY is
begin
process(d)
begin
case d is
when"0000" =>q<="0111111";
when"0001" =>q<="0000110";
when"0010" =>q<="1011011";
when"0011" =>q<="1001111";
when"0100" =>q<="1100110";
when"0101" =>q<="1101101";
when"0110" =>q<="1111101";
when"0111" =>q<="0100111";
when"1000" =>q<="1111111";
when others =>q<="1101111";
end case;
end process;
end disp_are;
-----7.定时闹钟模块程序
library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);
clk:in std_logic;
q500,qlk:out std_logic);
end ALERT;
architecture sss_arc of ALERT is
begin
process(clk)
begin
if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then
q500<='1';
else
q500<='0';
end if;
end if;
if m1="0101" and m0="1001" and s1="0101" and s0="1001" then
qlk<='1';
else
qlk<='0';
end if;
end if;
end process;
end sss_arc;
Architecture one of topclock is
Component second1
Port( clks,clr:in std_logic;
secs,secg: buffer std_logic_vector(3 downto 0);
cout1: out std_logic);
End Component;
Component min1
Port(clkm,clr:in std_logic;
mins,ming:buffer std_logic_vector(3 downto 0);
enmin,alarm: out std_logic);
End Component;
Component hour1
Port(clkh,clr:in std_logic;
hours,hourg:buffer std_logic_vector(3 downto 0));
End Component;
Component madapt
Port(en,m1,clk,secin:in std_logic;
minset:out std_logic);
End Component;
Component hadapt
Port(en,h1,clk,minin:in std_logic;
hourset:out std_logic);
End Component;
signal a,b,c,d: std_logic;
begin
u1:second1 port map(clr=>clr,
secs=>secs,secg=>secg,clks=>clk, cout1=>a);
u2:min1 port map(clr=>clr,alarm=>alarm,
mins=>mins,ming=>ming,clkm=>b,enmin=>c);
u3:hour1 port map(clr=>clr,
hours=>hours,hourg=>hourg,clkh=>d);
u4:madapt port map(en=>en,m1=>m1,clk=>clk,secin=>a,minset=>b);
u5:hadapt port map(en=>en,h1=>h1,clk=>clk,minin=>c,hourset=>d);
end;
③ 基于eda的30秒倒计时程序设计
给你一个10进制程序参考一下：
CLK，
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dcnt10 IS
PORT(ena,load,clk:IN STD_LOGIC;
datein:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cq:OUT STD_LOGIC_VECTOR(3 DOWNTO 0););
END dcnt10;
ARCHITECTURE one OF dcnt10 IS
SIGNAL cq1:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk,ena)IS
BEGIN
IF CLK'EVENT AND clk='1' THEN
IF ena='1'THEN
IF cq1="0000"THEN cq1<="1001";
ELSE cq1<=cq1-1;
END IF;
END IF;
END IF;
END PROCESS;
cq<=cq1;
④ 急！EDA程序设计改错问题，万分感谢!
好多地方都有问题。。。改正后如下：
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY abc IS
PORT (clk, rst : IN STD_LOGIC;
load,EN : IN STD_LOGIC;
din : IN STD_LOGIC_vector (7 downTO 0);
qb : out STD_LOGIC);
END abc;
ARCHITECTURE one OF abc IS
signal reg : STD_LOGIC_vector(7 downTO 0);
begin
PROCESS(rst,load,EN,clk)
BEGIN
IF rst='1' THEN
reg <= "00000000";
ELSIF rising_edge(clk) THEN
IF load = '1' THEN
reg <= din;
ELSIF EN='1' THEN
reg(6 downTO 0) <= reg(7 downTO 1);
END IF;
END IF;
END PROCESS;
qb <= reg(1);
END one;