A. 高分求VHDL編寫的分頻器程序
你這個是5分頻。
給你個萬能分頻程序吧！以後就不用問別人了！
VHDL的任意整數且占空比為%分頻代碼
說明如下：
1.其中top file 為 division，其中的clk_com是比較的頻率，用它來和分頻後波形進行比較，便於觀察，
2.any_enve為任意偶數分頻文件
3.any_odd為任意奇數分頻文件
4.是一個用於2進制與8進制的解碼器，我用它來顯示在數碼管上當前到底是多少分頻
5.以下代碼在開發板上實驗過，請大家放心使用，歡迎轉載，但請註明出處，另外說明由於用的是quartus7.1編輯的，中間無法加中文注釋，請大家慢慢讀了；以下是代碼：
------the top file of the design division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division is
port (input : in std_logic_vector(7 downto 0);
clk : in std_logic;
clk_out : out std_logic;
clk_com : out std_logic;
led1: out std_logic_vector(6 downto 0);
led2: out std_logic_vector(6 downto 0);
led3: out std_logic_vector(6 downto 0));
end entity division;
--------------------------------------------------
architecture freq of division is
component decoder is----decoder
port(bin : in std_logic_vector(2 downto 0);
de : out std_logic_vector(6 downto 0));
end component;
component any_even is----any_even division
generic (data_width : integer := 8 );
port(input1 : in std_logic_vector(data_width-1 downto 0);
clk_in : in std_logic;
clk_out : out std_logic);
end component any_even;
component any_odd is-----any_even division
generic (data_width : integer := 8);
port(input2 : in std_logic_vector(data_width - 1 downto 0);
clk_in : in std_logic;
clk_out : out std_logic);
end component any_odd;
signal temp1,temp2 : std_logic;
begin
u1: decoder port map(bin=>input(2)&input(1)&input(0),de=>led1);
u2: decoder port map(bin=>input(5)&input(4)&input(3),de=>led2);
u3: decoder port map(bin=>'0'&input(7)&input(6),de=>led3);
u4: any_even port map(input,clk,temp1);
U5: any_odd port map(input,clk,temp2);
process(clk,input)
begin
if input(0)= '0' then
clk_out <= temp1;
else clk_out <= temp2;
end if;
end process;
clk_com <= clk;
end architecture freq;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity any_even is
generic (data_width : integer := 8 );
port(input1 : in std_logic_vector(data_width-1 downto 0);
clk_in : in std_logic;
clk_out : out std_logic);
end entity any_even;
architecture div1 of any_even is
signal clk_outQ : std_logic ;
signal coutQ : std_logic_vector (data_width - 1 downto 0);
begin
-------------------------------------------------
process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if coutQ < (conv_integer(input1) - 1) then
coutQ <= coutQ + 1;
else coutQ <= (others => '0');
end if;
end if;
end process;
---------------------------------------------------
process(coutQ)
begin
if coutQ < (conv_integer(input1))/2 then
clk_outQ <= '0';
else clk_outQ <= '1';
end if;
end process;
clk_out <= clk_outQ;
end architecture div1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity any_odd is
generic (data_width : integer := 8);
port(input2 : in std_logic_vector(data_width - 1 downto 0);
clk_in : in std_logic;
clk_out : out std_logic);
end entity any_odd;
architecture div2 of any_odd is
signal cout1,cout2 : std_logic_vector(data_width - 1 downto 0);
signal clk1,clk2 : std_logic;
begin
process(clk_in)------rising edge
begin
if clk_in'event and clk_in='1' then
if cout1 < (conv_integer(input2)-1) then
cout1 <= cout1 + 1;
else cout1 <= (others => '0');
end if;
if cout1 < (conv_integer(input2)-1)/2 then
clk1 <= '1';
else clk1 <= '0';
end if;
end if;
end process;
---------------------------
process(clk_in)------falling edge
begin
if clk_in'event and clk_in='0' then
if cout2 < (conv_integer(input2)-1) then
cout2 <= cout2 + 1;
else cout2 <= (others => '0');
end if;
if cout2 < (conv_integer(input2)-1)/2 then
clk2 <= '1';
else clk2 <= '0';
end if;
end if;
end process;
clk_out <= clk1 or clk2;
end architecture div2;
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(bin : in std_logic_vector(2 downto 0);
de : out std_logic_vector(6 downto 0));
end entity;
----------------------------------------------------
architecture deco of decoder is
begin
process(bin)
begin
case bin is
when "000" => de <= "0111111";---0
when "001" => de <= "0000110";---1
when "010" => de <= "1011011";---2
when "011" => de <= "1001111";---3
when "100" => de <= "1100110";---4
when "101" => de <= "1101101";---5
when "110" => de <= "1111101";---6
when others => de <= "0000111";---7
end case;
end process;
end architecture;
B. VHDL編寫分頻器
library ieee;
use ieee.std_logic_1164.all;
entity oneMHZ is
port( clkin:in std_logic; --時鍾信號輸入
clkout:out std_logic); --時鍾信號輸出
end oneMHZ;
architecture aroneMHZ of oneMHZ is
signal data:integer range 0 to 10;
signal Q:std_logic;
begin
process(clkin)
begin
if rising_edge(clkin) then
if(data=0) then －－此句為你想要的分版頻權比，data=0,1,2,3,4.......9的分頻比為1,2，3，，,10
data<=0;
Q<=not Q;
else
data<=data+1;
end if;
end if;
clkout<=Q;
end process;
end oneMHZ;
C. 設計一個非同步清零的占空比為5/9的分頻器，寫出VHDL設計代碼
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mux6_1 is
port(
clk:IN std_logic;
rst:IN std_logic;
div9:out std_logic
);
end;
architecture behave of mux6_1 is
signal cnt: integer range 0 to 8;
signal temo_div9: std_logic;
begin
process(clk,rst)
if rst='0' then
if clk'event and clk='1' then
cnt <= cnt +1;
if cnt = 4 then
temp_div9 <= ~_div9;
elsif cnt = 8 then
cnt <= 0;
temp_div9 <= ~temp_div9;
end if;
end if;
end if;
end process;
div9 <= temp_div9;
end behave;